Simulator logičnih vrat

zaključno delo

Sandi Zakošek (Author), Domen Mongus (Mentor), Marko Bizjak (Co-mentor)

Abstract

Zaradi pomembnosti logičnih vezij dandanes obstaja veliko različnih spletnih in namiznih aplikacij (na primer simulator.io, Logicly, The Logic Lab), ki nam omogočajo simuliranje njihovega delovanja. Večina obstoječih simulatorjev je osnovanih tako, da na osnovi izbranih vhodnih vrednosti simulirajo izhode izbranega logičnega vezja. Čeprav je to razumljivo, saj se lahko več vhodov v logično vezje preslika v enak izhod, zgolj enosmerna simulacija omejuje možnosti obratnega inženirstva. V diplomskem delu naslovimo ta izziv, z razvojem algoritma, ki je zmožen analizirati izbrano logično vezje in ob podanih izhodnih vrednostih ovrednotiti pravilne vhodne vrednosti. Izdelan simulator omogoča izbor logičnih vrat in sekvenčnih vezij, na osnovi tega pa ovrednoti vhodne vrednosti za želen rezultat na izhodu. Pravilnost delovanja simulatorja smo preverili s kombiniranjem izbir, pri čemer smo ovrednotili tudi hitrost delovanja.

Keywords

logična vrata;sekvenčno vezje;obratno inženirstvo;logične funkcije;algoritmi;diplomske naloge;

Data

Language:	Slovenian
Year of publishing:	2019
Typology:	2.11 - Undergraduate Thesis
Organization:	UM FERI - Faculty of Electrical Engineering and Computer Science
Publisher:	[S. Zakošek]
UDC:	004.94:004.312.22(043.2)
COBISS:	22577686
Views:	1320
Downloads:	123
Average score:	0 (0 votes)
Metadata:

Other data

Secondary language:	English
Secondary title:	Logic gate simulator
Secondary abstract:	Due to the importance of the logic circuits, there are many different web and desktop applications available on the market today. They give the option to perform a simulation of their operation (e.g. Simulator.io, The logic Lab). Most of these applications are simulating outputs of the selected logic circuits, determined by the selected input values. Although this is understandable since multiple inputs into the logic circuit can be mapped to the same output, this type of simulation, which works only one-way, limits the possibilities of reverse engineering. In the thesis, we address this challenge by developing an algorithm that is able to analyze the selected logic circuit as well as evaluate the correct input values, at given output values. Our simulator enables a set of logic doors and sequential circuits. On this grounds, it evaluates the input values in order to get the desired results at the output. We performed various tests of the simulator through a combination of different output values options, in conjunction to the evaluation of the speed of it's operation.
Secondary keywords:	Logic gates;sequential circuit;reverse engineering;logic functions;algorithm;
Type (COBISS):	Bachelor thesis/paper
Thesis comment:	Univ. v Mariboru, Fak. za elektrotehniko, računalništvo in informatiko, Računalništvo in informacijske tehnologije
Pages:	VIII, 42 str.
ID:	11143878