ǂA ǂbinary neural network on an FPGA

bachelor's thesis

Klara Langerholc (Author), Uroš Lotrič (Mentor), Anton Biasizzo (Co-mentor), Dong Seog Han (Co-mentor)

Abstract

In recent years, the performance of convolutional neural networks has been increasing rapidly. But higher performance brings higher computational and memory costs. Research has shown that good accuracy can be achieved even when operands are constrained to only one or two bits. The purpose of this work is to implement a binary neural network with operands constrained to one bit on a field-programmable gate array. The computations in binary neural networks are mostly binary, while the weights require very little memory, making them ideal for hardware implementation. The implemented network was tested on MIO-TCD database, while the implementation was mostly focused on resource consumption and speed.

Keywords

binary neural network;FPGA;Verilog;ZedBoard;computer science;computer and information science;diploma thesis;

Data

Language:	English
Year of publishing:	2020
Typology:	2.11 - Undergraduate Thesis
Organization:	UL FRI - Faculty of Computer and Information Science
Publisher:	[K. Langerholc]
UDC:	004.8(043.2)
COBISS:	32142083
Views:	740
Downloads:	204
Average score:	0 (0 votes)
Metadata:

Other data

Secondary language:	Slovenian
Secondary title:	Binarna nevronska mreža na programirljivem vezju FPGA
Secondary abstract:	V zadnjih letih se zmogljivosti konvolucijskih nevronskih mrež neprestano povečujejo. Vendar pa se z zmogljivostjo povečuje tudi kompleksnost mrež in s tem poraba računskih virov in virov za shranjevanje uteži. Raziskave so pokazale, da je pri mnogih problemih zadovoljivo delovanje nevronskih mrež doseženo tudi z le enobitnimi ali dvobitnimi operandi. V tem delu smo binarno konvolucijsko mrežo implementirali na reprogramirljivem vezju FPGA. Računske operacije v binarnih mrežah so večinoma binarne, za shranjevanje uteži pa se potrebuje malo prostora, kar jih naredi idealne za implementacijo v strojni opremi. Implementirano mrežo smo testirali na bazi slik MIO-TCD, pri imlementaciji pa smo bili pozorni predvsem na porabo virov in hitrost izvedbe.
Secondary keywords:	binarna nevronska mreža;FPGA;Verilog;ZedBoard;računalništvo in informatika;univerzitetni študij;diplomske naloge;
Type (COBISS):	Bachelor thesis/paper
Study programme:	1000468
Embargo end date (OpenAIRE):	1970-01-01
Thesis comment:	Univ. v Ljubljani, Fak. za računalništvo in informatiko
Pages:	53 str.
ID:	12038968