magistrsko delo
Qichao Chen (Author), Branko Šter (Mentor)

Abstract

Ker so tehnologije umetne inteligence vse bolj vključene v naše vsakdanje življenje, je učinkovito izvajanje nevronskih mrež na prenosnih in cenovno ugodnih napravah postalo pomembno področje raziskav. Zaradi visokih stroškov in porabe energije procesorji in grafični procesorji težko zadostijo tem zahtevam. V tej nalogi smo raziskali implementacijo konvolucijske nevronske mreže v vezju FPGA z uporabo visokonivojske sinteze. Visokonivojska sinteza sicer samodejno pretvori programsko kodo (npr., v jeziku C) v strojno-opisni jezik (HDL), kar bistveno skrajša razvojni cikel, vendar pa je lahko taka implementacija še daleč od optimalne. Zato mora razvijalec z uporabo posebnih direktiv poskrbeti za ustrezno uporabo različnih vrst paralelizacije, kar pa se pri bolj kompleksnih vezij izkaže za netrivialno. Predlagali smo metriko učinkovitosti optimizacijske strategije, ki meri razmerje med pohitritvijo in porabo virov ter omogoča oceno strategij za posamezne plasti konvolucijske nevronske mreže. Na podlagi teh ocen smo z modelom linearnega programiranja izbrali optimizacijske strategije za izboljšanje zmogljivosti celotne nevronske mreže. Naša implementacija na FPGA je pri frekvenci 50 MHz dosegla čas izvajanja 4 ms, kar presega zmogljivost običajnega procesorja pri 3200 MHz, in pokazala prednosti v energetski učinkovitosti.

Keywords

vezja FPGA;visokonivojska sinteza;konvolucijske nevronske mreže;magisteriji;

Data

Language: Slovenian
Year of publishing:
Typology: 2.09 - Master's Thesis
Organization: UL FRI - Faculty of Computer and Information Science
Publisher: [Qichao Chen]
UDC: 004.032.26:004.8(043.2)
COBISS: 210470915 Link will open in a new window
Views: 90
Downloads: 1172
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Other data

Secondary language: English
Secondary title: Convolutional neural network implementation with high-level synthesis on an FPGA
Secondary abstract: As artificial intelligence technologies are increasingly integrated into our daily lives, the efficient implementation of neural networks on portable and affordable devices has emerged as a crucial research area. Due to the high costs and energy consumption, CPUs and GPUs struggle to meet these demands. This study explored implementing a convolutional neural network on an FPGA using high-level synthesis (HLS). While high-level synthesis automatically converts programming code (e.g., in C language) into a hardware description language (HDL), and significantly shortens the development cycle, such implementation may still be far from optimal. Therefore, the developer must use specific directives to ensure appropriate utilization of various types of parallelization, which proves to be non-trivial for more complex circuits. We proposed a metric for the efficiency of the optimization strategy, measuring the ratio between speedup and resource consumption, allowing for evaluating strategies for individual layers of the convolutional neural network. Based on these evaluations, we used a linear programming model to select optimization strategies to improve the overall neural network's performance. Our FPGA implementation achieved a runtime of 4 ms at a frequency of 50 MHz, outperforming a conventional processor operating at 3200 MHz, and demonstrated advantages in energy efficiency.
Secondary keywords: FPGA circuits;high-level synthesis;convolutional neural networks;artificial intelligence;computer science;master's degree;Nevronske mreže (računalništvo);Umetna inteligenca;Računalništvo;Univerzitetna in visokošolska dela;
Type (COBISS): Master's thesis/paper
Study programme: 1000471
Embargo end date (OpenAIRE): 1970-01-01
Thesis comment: Univ. v Ljubljani, Fak. za računalništvo in informatiko
Pages: 1 spletni vir (1 datoteka PDF (81 str.))
ID: 25170647