magistrsko delo
Uroš Sadek (Author), Rajko Svečko (Mentor), Andrej Sarjaš (Co-mentor)

Abstract

V sledečem magistrskem delu, smo se posvetili izdelavi eksperimentalnega sistema za izvedbo in testiranje robustnega vodenja DC-DC pretvornika navzgor, s pomočjo programirljivega polja logičnih vrat (FPGA – Field Programmable Gate Array). Robustnost pretvornika, se kaže v stabilni izhodni napetosti ob spreminjajoči impedanci bremena. Pri načrtovanju vodenja, smo uporabili linearni matematični modela pretvornika z dano nominalno karakteristiko bremena. Eksperimentalni sistem zajema DC-DC pretvornik ter nelinearno impedančno spremenljivo breme, s katerim smo pretvornik obremenili. Breme je načrtovano tako, da je mogoče spreminjati značaj bremena med induktivnim, kapacitivnim in uporovnim značajem.

Keywords

robustnost;vodenje;pretvorniki navzgor;FPGA;

Data

Language: Slovenian
Year of publishing:
Typology: 2.09 - Master's Thesis
Organization: UM FERI - Faculty of Electrical Engineering and Computer Science
Publisher: [U. Sadek]
UDC: 681.51:621.314.1.049(043.2)
COBISS: 18438166 Link will open in a new window
Views: 1330
Downloads: 139
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Other data

Secondary language: English
Secondary title: ROBUST CONTROL OF DC-DC BOOST CONVERTER WITH CHANGEABLE LOAD IMPEDANCE
Secondary abstract: In this thesis, focus was on designing and creating of an experimental system, which will allow us to design and test all kind of robust control algorithms of DC-DC boost converter with FPGA (Field Programmable Gate Array). Robustness of such a converter is reflected in output voltage stability, when load with changeable impedance in specified limits, is turned on and off. In control design, a known linear model of converter has been used. Experimental system covers a DC-DC boost converter and load with changeable impedance. Load has been designed in such way, it is possible to change between resistive, capacitive and inductive load characteristics.
Secondary keywords: robust;control;boost converter;load impedance;FPGA;
URN: URN:SI:UM:
Type (COBISS): Master's thesis/paper
Thesis comment: Univ. v Mariboru, Fak. za elektrotehniko, računalništvo in informatiko, Elektronika
Pages: VIII, 80 str.
ID: 8730430
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