Implementacija procesorja po specifikaciji RISC-V v vezju FPGA

diplomsko delo

Mitja Tišler (Author), Patricio Bulić (Mentor)

Abstract

Večina danes najbolj uporabljanih ukaznih arhitektur je lastniških, kar predstavlja oviro za njihovo uporabo v znanosti, raziskavah in izobraževanju. Poleg tega te arhitekture zaradi združljivosti z njihovimi preteklimi različicami niso optimalne. RISC-V je za razliko od teh odprtokodna ukazna arhitektura in je zasnovana modularno, z obvezno uporabo ene od štirih baznih različic in z opcijskimi razširitvami. V diplomskem delu smo procesor s to ukazno arhitekturo opisali v strojno-opisnem jeziku VHDL in implementirali v vezju FPGA, pojasnili razloge za izbrane načrtovalske odločitve ter preizkusili zmogljivost implementacije. Procesor je možno programirati prek vmesnika UART, medtem ko vsebino programsko dostopnih registrov prikazujemo na zaslonu s pomočjo krmilnika VGA.

Keywords

RISC-V;FPGA;digitalno načrtovanje;VHDL;univerzitetni študij;diplomske naloge;

Data

Language:	Slovenian
Year of publishing:	2023
Typology:	2.11 - Undergraduate Thesis
Organization:	UL FRI - Faculty of Computer and Information Science
Publisher:	[M. Tišler]
UDC:	004(043.2)
COBISS:	153493251
Views:	41
Downloads:	10
Average score:	0 (0 votes)
Metadata:

Other data

Secondary language:	English
Secondary title:	Implementation of RISC-V processor in FPGA
Secondary abstract:	Most commonly used instruction set architectures are proprietary, which prevents them from being used in science, research and education. These architectures are also not optimal, because of compatibility issues. RISC-V is on the other hand, modular open-source instruction set architecture, with compulsory use of one of four base instruction set variants and with optional extensions. As part of the diploma thesis, we specified FPGA configuration of RISC-V based processor in VHDL, explained design choices and tested developed specification on the FPGA board. Programs can be loaded to processor over UART, while content of the general purpose registers can be shown on the VGA display.
Secondary keywords:	RISC-V;FPGA;digital design;VHDL;computer and information science;diploma;Univerzitetna in visokošolska dela;
Type (COBISS):	Bachelor thesis/paper
Study programme:	1000468
Embargo end date (OpenAIRE):	1970-01-01
Thesis comment:	Univ. v Ljubljani, Fak. za računalništvo in informatiko
Pages:	25 str.
ID:	19002147